Appendix D Reading the Intel and AMD manuals

Every chapter of Part III, and several of Parts I and II, sends you to a precise section of a vendor manual before explaining the difficult parts. This appendix collects those pointers in one place, in reading order, and adds for each the equivalent section of the other vendor’s manual, so that a reader who owns an AMD machine, or who simply prefers the AMD text, can follow the book from either. It is a collation: nothing here is explained, and a row that cites a section means “read it before the chapter”, not “the chapter paraphrases it”.

D.1 How the two manual sets are organized

Intel publishes the Intel 64 and IA-32 Architectures Software Developer’s Manual (SDM) (Intel 2016) in four volumes, each split into parts that are also sold as separate PDFs:

AMD publishes the AMD64 Architecture Programmer’s Manual (APM) in five volumes, numbered by publication: Volume 1, Application Programming (24592), Volume 2, System Programming (24593) (AMD 2026a), Volume 3, General-Purpose and System Instructions (24594) (AMD 2026b), Volume 4, 128-Bit, 256-Bit and 512-Bit Media Instructions (26568), and Volume 5, 64-Bit Media and x87 Floating-Point Instructions (26569); a single PDF of all five is publication 40332. Volume 1 corresponds to Intel’s Volume 1, Volume 2 to Intel’s Volume 3, and Volumes 3 to 5 together to Intel’s Volume 2, with the instruction reference split by category rather than in one alphabet. The MSRs have no volume of their own: they are Appendix A of Volume 2. Volume 2 is organized by mechanism in the same spirit as Intel’s 3A, with different names: segmented virtual memory (chapter 4) for protected-mode memory management, page translation and protection (chapter 5) for paging, exceptions and interrupts (chapter 8), task management (chapter 12), and processor initialization and long mode activation (chapter 14), where AMD, who designed long mode, documents it first. AMD calls real mode, protected mode and virtual-8086 mode together legacy mode (section 1.3.4), as opposed to long mode (1.3.1), and its chapter 2, “x86 and AMD64 Architecture Differences”, is a twenty-page summary of what long mode changed that has no Intel counterpart and is worth reading on its own.

Three practical rules for navigating them:

  1. Search by section title, not number. Intel renumbers the chapters of Volume 3A between editions: between the 2016 edition the first edition of this book used and the September 2026 edition this one cites, “Paging” moved from chapter 4 to 5 and “Task Management” from 7 to 10, and section numbers move with them (Appendix A gives the editions). The AMD numbering has been stable for twenty years, but AMD titles differ from Intel’s for the same thing, so a title search needs the AMD vocabulary: “page translation” rather than “paging”, “descriptor” rather than “gate” in some places, “control transfer” rather than “handler procedure”. The tables below give both titles.
  2. Both manuals cross-reference by figure. Every data structure the kernel builds in Part III (descriptor, gate, TSS, page-table entry, interrupt frame) has one figure in each manual, and the figure, not the prose, is what you translate into a C struct. The AMD manual cites its own figures by page (“see ‘Code-Segment Descriptors’ on page 98”); the Intel manual by number.
  3. Download the current edition and keep it. Both are free: Intel’s are on the “Intel SDM” page of its developer site, as the combined PDF or one volume at a time; AMD’s are found by searching the publication number on AMD’s documentation portal. Editions change under their URLs, so note the revision on the title page (the Intel revision is the three-digit number after the order number; the AMD revision is on the first page, “24593 3.45 July 2026” for the Volume 2 cited here). The numbers in this book are those of the Intel edition of September 2026 and of APM Volume 1 revision 3.25, Volume 2 revision 3.45 and Volume 3 revision 3.38.

The tables use “SDM” for the Intel manual with the volume as cited in the chapters (1, 2, 3A, 3C, 4) and “APM” for the AMD manual with its volume (1, 2, 3). Where a chapter cites a document that is not a vendor manual (the ELF and DWARF specifications, the ATA standard, the ext2 layout, the ACPI specification), the row says so, and the AMD column is empty when the material is vendor-independent.

D.2 Part I: the hosted programs

chapter Intel SDM: read before the chapter AMD APM equivalent
3, Computer architecture Volume 1, chapter 3 “Basic Execution Environment”: 3.1 modes of operation, 3.4.1 general-purpose registers, 3.4.2 segment registers, 3.4.3 EFLAGS, 3.5 instruction pointer. Volume 3A, 2.1 “Overview of the System-Level Architecture”, 2.2 “Modes of Operation”, 2.3 “System Flags and Fields in the EFLAGS Register”, 2.5 “Control Registers”, 3.4.2 and 3.4.3 (selectors and segment registers), 6.5 “Privilege Levels”. Volume 1, chapter 1 “Overview of the AMD64 Architecture” (1.2 modes of operation), chapter 2 “Memory Model” (2.1 memory organization, 2.5 instruction pointer), 3.1 “Registers” (3.1.1 legacy registers, 3.1.4 flags register, 3.1.5 instruction pointer register). Volume 2, chapter 1 “System-Programming Overview” (1.3 “Operating Modes”, figure 1-6; 1.4 “System Registers”), 3.1 “System-Control Registers” (3.1.1 CR0, 3.1.6 RFLAGS), 4.5 “Segment Selectors and Registers”, 4.9 “Segment-Protection Overview” (4.9.1 privilege-level concept).
4, x86 assembly and C Volume 2, 2.1 “Instruction Format” and, from chapter 3 on, the reference page of each instruction the chapter uses (mov, push, call, ret, lea, the jumps). Volume 3, chapter 1 “Instruction Encoding”, chapter 2 “Instruction Overview” (2.2 reference-page format, 2.5 notation), chapter 3 “General-Purpose Instruction Reference” for the same instructions. Volume 1, 3.3 “Instruction Summary”, 3.7 “Control Transfers” (3.7.3 procedure stack, 3.7.5 procedure calls). The calling convention is in the System V ABI i386 supplement, not in either manual.
5, Anatomy of a program None. The reference is the ELF specification (System V ABI, chapter 4 “Object Files”: ELF header, sections, string and symbol tables; chapter 5 “Program Loading”, program headers), which man 5 elf reproduces. None: ELF is vendor-independent. The x86 details (relocation types) are in the i386 and x86-64 psABI supplements, maintained outside both vendors.
6, Runtime inspection and debugging Volume 3A, 2.3 (the trap flag and the system flags gdb manipulates). The debugging-information format is the DWARF standard (version 4 or 5: chapter 2 “General Description”, chapter 3 “Program Scope Entries”, 6.2 “Line Number Information”, chapter 7 “Data Representation”). Volume 2, 3.1.6 “RFLAGS Register” and, for the hardware side of breakpoints the chapter mentions, chapter 13 “Software Debug and Performance Resources”. DWARF is vendor-independent.

D.3 Part II: the bootloader

chapter Intel SDM: read before the chapter AMD APM equivalent
7, Bootloader Nothing is cited: the chapter runs in real mode and uses BIOS services, documented in Ralf Brown’s Interrupt List (INT 10h, INT 13h). Background: Volume 3A, 12.1.1 “Processor State After Reset” and 23.1 “Real-Address Mode” (chapter 23, “8086 Emulation”). Volume 2, 4.1 “Real Mode Segmentation”, 8.6 “Real-Mode Interrupt Control Transfers”, 14.1.3 “Processor Initialization State”.
8, Linking and loading None from the SDM. ELF specification, chapter 4 (relocation entries and types) and chapter 5 (“Program Header”, PT_LOAD and PT_PHDR, “Program Loading”); the i386 psABI for R_386_32 and R_386_PC32. None: vendor-independent.

D.4 Part III: the kernel

chapter Intel SDM: read before the chapter AMD APM equivalent
9, Protected mode and descriptors Volume 3A, chapter 3 “Protected-Mode Memory Management”: 3.4.2 “Segment Selectors”, 3.4.3 “Segment Registers”, 3.4.5 “Segment Descriptors” and 3.4.5.1 “Code- and Data-Segment Descriptor Types”, 3.5.1 “Segment Descriptor Tables”; 2.4.1 “Global Descriptor Table Register (GDTR)”, 2.5 “Control Registers”; chapter 6 “Protection” (6.5 privilege levels); 12.1.1 “Processor State After Reset”, 12.9 “Mode Switching” and 12.9.1 “Switching to Protected Mode”. Volume 2, chapter 4 “Segmented Virtual Memory”: 4.5.1 “Segment Selectors”, 4.5.2 “Segment Registers”, 4.6.1 “Global Descriptor Table”, 4.6.2 “Global Descriptor-Table Register”, 4.7 “Legacy Segment Descriptors” (4.7.1 descriptor format, 4.7.2 code-segment and 4.7.3 data-segment descriptors), 4.9 “Segment-Protection Overview”; 3.1.1 “CR0 Register” (the PE bit; AMD has no separate “switching to protected mode” section, the switch is the PE bit and the descriptor chapter); 14.1.3 “Processor Initialization State”.
10, Devices: serial and VGA Volume 1, chapter 20 “Input/Output”: 20.1 “I/O Port Addressing”, 20.4 “I/O Instructions”, 20.5 “Protected-Mode I/O”. The devices themselves are in the 16550 and VGA documentation, not in the SDM. Volume 1, 3.8 “Input/Output” (3.8.1 “I/O Addressing”, 3.8.3 “Protected-Mode I/O”); Volume 2, 7.9 “Memory-Mapped I/O” for the VGA buffer.
11, Interrupts Volume 3A, chapter 7 “Interrupt and Exception Handling”: Table 7-1 “Protected-Mode Exceptions and Interrupts”, 7.8 “Enabling and Disabling Interrupts”, 7.10 “Interrupt Descriptor Table (IDT)”, 7.11 “IDT Descriptors” with figure 7-2 “IDT Gate Descriptors” (figure 6-2 in the 2016 edition, the number chapter 11 uses), 7.12.1 “Exception- or Interrupt-Handler Procedures” and 7.12.1.3 “Flag Usage By Exception- or Interrupt-Handler Procedure”, 7.13 “Error Code”; 2.4.3 “IDTR Interrupt Descriptor Table Register”. The 8259A and the 8253/8254 are in their own datasheets. Volume 2, chapter 8 “Exceptions and Interrupts”: Table 8-1 “Interrupt Vector Source and Cause”, 8.1.4 “Masking External Interrupts”, 8.2 “Vectors” (one subsection per exception), 8.4 “Error Codes”, 8.7 “Legacy Protected-Mode Interrupt Control Transfers” (8.7.1 locating the handler, 8.7.2 and 8.7.3 same and higher privilege, 8.7.5 returning); 4.6.5 “Interrupt Descriptor Table”, 4.6.6 “Interrupt Descriptor-Table Register”, 4.7.5 “Gate Descriptors”.
12, Memory management Volume 3A, chapter 5 “Paging”: 5.1 “Paging Modes and Control Bits”, 5.3 “32-Bit Paging” (Table 5-3 CR3, Tables 5-5 and 5-6 page-directory and page-table entries), 5.6 “Access Rights”, 5.7 “Page-Fault Exceptions” and figure 5-12 “Page-Fault Error Code”, 5.10.4 “Invalidation of TLBs and Paging-Structure Caches”. The E820 memory map is in the ACPI specification, chapter 15 “System Address Map Interfaces”. Volume 2, chapter 5 “Page Translation and Protection”: 5.1 “Page Translation Overview” (5.1.2 PG bit), 5.2.2 “Normal (Non-PAE) Paging” (figures 5-5 and 5-6), 5.4 “Page-Translation-Table Entry Fields”, 5.6 “Page-Protection Checks”, 5.5.3 “TLB Management”; 3.1.2 “CR2 and CR3 Registers”; 8.2.15 “#PF—Page-Fault Exception (Vector 14)”, 8.4.2 “Page-Fault Error Code”; 6.6.2 “TLB Invalidation” (invlpg).
13, Processes Volume 3A, chapter 10 “Task Management”: 10.2.1 “Task-State Segment (TSS)”, 10.2.4 “Task Register”; chapter 6 “Protection”: 6.5 “Privilege Levels”, 6.6 “Privilege Level Checking When Accessing Data Segments”; figure 7-4 “Stack Usage on Transfers to Interrupt and Exception-Handling Routines”; 3.5 “System Descriptor Types”; 7.12.1 and 7.12.1.2 “Protection of Exception- and Interrupt-Handler Procedures”; 5.7 and figure 5-12 (user-mode page faults). Volume 1, 3.4.3 (the IOPL field), 20.5 “Protected-Mode I/O” and 20.5.2 “I/O Permission Bit Map”. Volume 2, chapter 12 “Task Management”: 12.2.2 “TSS Descriptor”, 12.2.3 “Task Register”, 12.2.4 “Legacy Task-State Segment” (figure 12-7, I/O-permission bitmap); 4.9 to 4.11 (4.10 “Data-Access Privilege Checks”, 4.11 “Control-Transfer Privilege Checks”); 4.7.4 “System Descriptors”; 8.7.3 “Interrupt To Higher Privilege”, 8.7.4 “Privilege Checks”; 6.1 “Fast System Call and Return” for the alternative to int. Volume 1, 3.1.4 “Flags Register”, 3.8.3 “Protected-Mode I/O”.
14, File system Volume 3A, 5.3 (mapping the loaded program). ATA/ATAPI-6: 3.2.9, 7.2, 7.3, 7.7 (the drive/head register), 7.15.6, 8 and 8.15 (the IDENTIFY DEVICE and READ SECTOR(S) commands); the ext2 layout document by Dave Poirier. Volume 2, 5.2.2. The disk and the filesystem are vendor-independent.
15, Address spaces: fork and exec Volume 3A, 5.3 again (one page directory per process) with Tables 5-5 and 5-6 (the “Ignored” bits 11:9 of an entry, where the copy-on-write mark lives); 5.1.3 “Paging-Mode Modifiers” and 2.5 “Control Registers” (CR0.WP), 5.6 “Access Rights”; 5.7 “Page-Fault Exceptions” and figure 5-12 again (P = 1, W/R = 1); 5.10 “Caching Translation Information”, 5.10.2 “Translation Lookaside Buffers (TLBs)” with 5.10.2.3 “Details of TLB Use” (no TLB entry for a not-present page, so demand paging needs no invlpg), 5.10.4 “Invalidation of TLBs and Paging-Structure Caches” with 5.10.4.1 (what a mov cr3 invalidates and what invlpg is for) and 5.10.4.2 “Recommended Invalidation”; 5.10.5 “Propagation of Paging-Structure Changes to Multiple Processors” for later. Volume 2, 5.4.1 “Field Definitions” (the AVL bits), 5.5 “Translation-Lookaside Buffer (TLB)”, 5.5.3 “TLB Management”, 6.6.2 “TLB Invalidation”, 3.1.1 “CR0 Register” and 5.6.4 “Write Protect (CR0.WP) Bit”, 3.1.2 “CR2 and CR3 Registers”, 5.6 “Page-Protection Checks” with 5.6.1 “User/Supervisor (U/S) Bit” and 5.6.2 “Read/Write (R/W) Bit”, 8.4.2 “Page-Fault Error Code”.
16, When it does not boot: debugging a kernel Volume 3A, 7.12.1 “Exception- or Interrupt-Handler Procedures” (the stack frame you read from $esp), 7.13 “Error Code” (decoding #GP error codes), 5.7 “Page-Fault Exceptions” with figure 5-12 (decoding #PF error codes and CR2), 7.15 “Exception and Interrupt Reference” (one entry per vector). Volume 2, 8.2 “Vectors” (per-vector descriptions), 8.4 “Error Codes” (selector and page-fault error codes), 8.7.2 and 8.7.3 (what is pushed on the stack with and without a privilege change).
17, Epilogue Volume 3A, 2.2 “Modes of Operation”, 2.2.1 “Extended Feature Enable Register”, 12.8.5 “Initializing IA-32e Mode”, 5.5 “4-Level Paging and 5-Level Paging”, 5.1.4 “Enumeration of Paging Features by CPUID”, 3.4.5 and 6.2.1 (the L bit), 7.14 “Exception and Interrupt Handling in 64-Bit Mode”, 6.8.7.1 and 6.8.8 “Fast System Calls in 64-Bit Mode”, chapter 11 “Multiple-Processor Management” (11.2 “Memory Ordering”, 11.4 “Multiple-Processor (MP) Initialization”, 11.9.2 topology), chapter 13 “Advanced Programmable Interrupt Controller (APIC)”; Volume 3C, chapters 26 to 33 (VMX); Volume 4 (MSRs). Volume 2, 1.3 “Operating Modes”, chapter 2 “x86 and AMD64 Architecture Differences”, 3.1.3 “CR4 Register”, 3.1.7 “Extended Feature Enable Register (EFER)”, 3.2 “Model-Specific Registers (MSRs)”, 4.8.1 “Code-Segment Descriptors”, 5.3 “Long-Mode Page Translation”, 6.1.1 “SYSCALL and SYSRET”, 6.1.2 “SYSENTER and SYSEXIT (Legacy Mode Only)”, 7.2 “Multiprocessor Memory Access Ordering”, 8.9 “Long-Mode Interrupt Control Transfers”, 12.2.5 “64-Bit Task State Segment”, 14.1.4 “Multiple Processor Initialization”, 14.6 “Enabling and Activating Long Mode”, chapter 15 “Secure Virtual Machine”, chapter 16 “Advanced Programmable Interrupt Controller (APIC)” (16.3.5, 16.5), Appendix A “MSR Cross-Reference”. Volume 3, Appendix E “Obtaining Processor Information Via the CPUID Instruction” (E.4.2, E.4.15, E.4.16).
Appendix C, A minimal long-mode bootstrap Volume 3A, 12.8.5 with 12.8.5.1 to 12.8.5.3, 2.2.1 and figure 2-4, 2.5, 2.8.10 “Reading and Writing Model-Specific Registers”, 3.4.5, 6.2.1 “Code-Segment Descriptor in 64-bit Mode”, 5.5.4 “Linear-Address Translation with 4-Level Paging and 5-Level Paging” with figure 5-9 and Tables 5-12, 5-15, 5-17, 5-18, 5-19, 5-20, 5.8 “Accessed and Dirty Flags”, 5.1.4, 7.14.1, 7.14.2, 10.7 “Task Management in 64-bit Mode”. Volume 2B, rdmsr, wrmsr, mov to and from control registers. Volume 2, 14.5 “Initializing Long Mode”, 14.6 to 14.6.3, 14.8 “Long-Mode Initialization Example”, Table 14-4 “Processor Operating Modes”, 3.1.3, 3.1.7 and figure 3-9, 3.2, 4.5.3 “Segment Registers in 64-Bit Mode”, 4.8.1 and figure 4-20, 5.3.2 “CR3”, 5.3.4 “2-Mbyte Page Translation” (figures 5-24 and 5-29), figures 5-20 to 5-23, 5.4.2 “Notes on Accessed and Dirty Bits”, 5.6.3 “No Execute (NX) Bit”, 8.4.2, 8.9.1, 8.9.3, 12.2.5. Volume 3, chapter 4 “System Instruction Reference”: MOV CRn, RDMSR, WRMSR; Appendix E.4.2.

Two remarks on using the tables. First, the Intel column lists what the chapter cites, in the order the chapter needs it, and the AMD column lists where the same material is; when the AMD column names more sections than the Intel one, it is because AMD spreads over several short sections what Intel puts in one, not because there is more to read. Second, the AMD manual documents long mode and legacy mode together in every chapter, with the legacy case usually second; when you look up a 32-bit mechanism of Part III, skip to the subsection whose title contains “legacy”.